Apparatus for synchronizing master and slave processors

ABSTRACT

A master and slave arrangement of processors includes a clock signal synchronization apparatus. The clock signals of two (processor) assemblies in micro-synchronous operation are only allowed to exhibit an extremely slight phase difference. A system clock signal is generated by a voltage controlled oscillator, which is fed by phase detectors with a filter at the output of each phase detector. Switches are provided between the filter output and the voltage controlled oscillator input. The phase detectors compare the system clock signal and a reference clock signal. A delay is provided at the input of one phase detector.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention related generally to a synchronization unit forsynchronizing two system clocks in an electronic device, such as aswitching device.

2. Description of the Related Art

For satisfying increased operational dependability in switchingtechnology, it is demanded that two processor assemblies (one of the twois a master and the other is a slave) work redundantly. This can beachieved by micro-synchronous operation, whereby the slave synchronizesto the master. The master in turn synchronizes to an external referenceclock. Given an outage of the external reference clock, the (clock)master must continue to work for example, in a (hold over mode) and theslave must continue to synchronize to the master.

The critical demand for micro-synchronous operation is that the phasedifference between the two processor assemblies should lie within anextremely slight time difference (for example, 5 ns).

Synchronization methods wherein phase information are exchanged betweenthe two processor assemblies can be imagined for satisfying the demand.In these methods, however, falsifications of the phase information canoccur due to different gate running times and reflections on theconnecting lines between the two assemblies. This leads to operatinginstabilities.

The European patent document EP 0 175 888 A discloses a synchronizationmeans using a phase comparator with each incoming channel to compare theclock phase of the incoming signal and a local oscillator. The phasecomparator of the active unit generates a signal to control theoscillator to maintain its output in phase with incoming signal. Theoscillator is a voltage controlled quartz oscillator.

SUMMARY OF THE INVENTION

The present invention is based on the object of providing asynchronization portion of an assembly that meets the demand forcollaboration with the synchronization portion of a partner assembly.

This object is achieved by a synchronization portion of an assembly thatgenerates the system clock of the assembly, whereby it synchronizes thesystem clock to one of several existing reference clocks, including,

a) a VCO that generates the system clock of the assembly depending on asignal applied to its control input;

b) an arrangement that includes a phase detector with a following filterand is present respectively once per reference clock signal, whereby arespective reference clock signal is applied to one input of a phasedetector and the system clock is respectively applied to the otherinput;

c) an operating control that controls the switches following the filterssuch that respectively one of the output signals of the filters isthrough-connected to the control input of the VCO, the operating controlcontrols further switches such that, given the arrangement wherein theoutput signal of the filter is not through-connected to the input of theVCO,

the output of the phase detector is switched to tri-state;

the output signal is fed back to the one filter input; and

the decoupled signal of the control input of the VCO is applied to theother filter input.

One embodiment of the invention provides a delay unit that delays thesystem clock before the input to the phase detector by the running timedifference between reference clock and system clock which makes itpossible to switch the mode of a processor assembly (for example, fromclock master to clock slave or vice versa) without leaving themicro-synchronous operation (slave/slave is not possible). The switchingis thus possible during micro-synchronous operation.

BRIEF DESCRIPTION OF THE DRAWINGS

An exemplary embodiment of the invention is explained in greater detailbelow with reference to the drawings.

FIG. 1 is a block diagram showing the synchronization system of thepresent invention in a master/slave processor arrangement;

FIG. 2 is functional block diagram of the synchronization portion;

FIG. 3 is a circuit diagram showing the activated operating mode;

FIG. 4 is a circuit diagram showing the standby mode; and

FIG. 5 is a circuit diagram showing the circuit in the monitor mode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows the basic structure of the mutual clock synchronization.According to the illustrated structure, a respective PLL is contained inan assembly, a switch that serves for switching between the operatingmodes "Master" and "Slave" of an assembly being present at the inputthereof.

Only one processor assembly is synchronized to the external referenceclock, namely the master assembly. The other processor assembly which isreferred to as the "Slave Assembly" synchronizes to the Master Processorassembly with a PLL (Phase Locked Loop). The Slave Processor assemblyruns with exactly the same frequency and phase as the Master Processorassembly.

FIG. 2 shows the basic structure of an inventive synchronization means.The synchronization means comprises

a voltage controlled oscillator VCO that generates the system clocksignal of the assembly dependent on a signal adjacent at its controlinput which here is a (set voltage input),

an arrangement that comprises a phase detector RV with a followingfilter (a loop filter) and that is provided for each reference clock,whereby a respective reference clock signal is at the one input R of aphase detector and the system clock is respectively adjacent at theother input V,

an operations controller (OC; can, for example, be realized by theprocessor of the assembly and/or by a corresponding logic) unit thatcontrols the switches following the filters such that respectively oneof the output signals of the filters is through-connected to the controlinput of the VCO,

a delay unit (shown as a delay line) that delays the system clockpreceding the input to the phase detector by the running time differencebetween the reference clock and the system clock.

The selection of the reference clocks by (analog) switches at the setvoltage input of the VCO (see FIG. 2) is for the following reason. Dueto the demand of a maximum 5 ns phase difference between the Master andthe Slave, no further running time of any switches whatsoever for theselection of an external reference clock is allowed preceding the inputof the phase comparator of the "Partner Processor Assembly" other thanthe line running time (the time difference between the minimum and themaximum running time of such a switch, namely, deteriorates the worstcase phase difference between the Master assembly and the Slaveassembly). A separate phase comparator is therefore inventively presentfor each reference clock.

The advantage of the structure shown in FIG. 2 compared to thearrangement shown in FIG. 1 wherein the switches are arranged at theinput of the PLLs is thus comprised therein that no further running timeof any switches whatsoever for the selection of an external referenceclock is added to the phase difference.

If the line running time makes an unacceptable difference with respectto the demand made of the phase time difference, this can be compensatedwith a lead of the PLL. To that end, a delay unit (which here is a delayline) is inserted preceding the comparison input V of the phase detectorof the Partner Processing Assembly that delays the system clockpreceding the input to the phase detector by the running time differencebetween the reference clock on the Master assembly and the system clockof the Slave assembly. Given employment of such a delay unit, what onethus achieves is that the reference clock and system clock (givenselection of a PLL that controls the phase difference at the phasedetector input to zero) are practically equiphase independently of therunning time difference.

In addition to controlling the switches shown in FIG. 2, the operatingcontrol also controls further switches (shown in FIGS. 3-5) such that,given a filter whose output signal is not through-connected to the inputof the VCO, the output signal is fed back to the one filter input andthe decoupled signal of the control input of the VCO is applied to theother filter input. As a result thereof, the output signal of apassively co-running loop filter is constantly regulated to the samelevel as that of the active arrangement. An optimum transient responseof the PLL phase skip thereby derives after the switching to a differentreference clock (external reference clock or system clock of the Partnerassembly)! A mode switching and/or a change of the external clock sourceis thus possible without deterioration of the micro-synchronousoperation.

The inventive clock synchronization works without exchange of the phaseinformation. This is achieved in that the line running time between thetwo processor assemblies is compensated with a lead of the PLL.

The selected PLL has a zero phase difference at the input of a phasedetector (PD) between the local clock and the external reference clock.

For example, the phase detector PD-Type 4 from Roland Best, Theorie undAnwendung des Phase-locked Loops, ISBN 3-85502-132-5 can be taken as aphase detector and can be easily modified so that it synchronizes to thepositive signal edge and the two outputs can be switched to tri-state.The advantage of this type is:

control to zero phase difference

phase and frequency-sensitive behavior

independence from supply voltage and temperature

easy realizability of the three phase comparators in one PLD(Programmable Logic Device)

great range of theoretical ±2π. This is necessary since the phase is notlost given switching to a different reference clock, i.e.synchronization is carried out to the original signal edge whenswitching back. This is necessary in order to prevent data loss at thesynchronous TSI interface.

Loop Filter:

Three loop filters having the following properties are realized:

A slow transient response is required when switching to an externalreference. The modulation of the set voltage input of the VCO musttherefore be small (small amplification) at the input phase skip.

A fast transient response is required when switching to the Partnerprocessor assembly. The modulation of the set voltage input of the VCOmust therefore be great (great amplification) at the input phase skip.

Different frequencies at the input of the three phase comparators,finally, likewise require correspondingly different dimensionings of theloop filters.

In order to prevent the loop filter output from leaving the range of theoperating voltage and proceeding into saturation (detent of the outputvoltage has a negative influence on the transient response of the PLL),there are three operating modes for each loop filter, these being shownin FIGS. 3-5 and being controlled by the operating control with theassistance of the illustrated switches.

FIG. 3 shows the activated operating mode:

In this operating mode, the PLL control circuit is closed (D1 and U1 arenot applied to tri-state). The processor assembly can thereby be inMaster mode or Slave mode.

FIG. 4 shows the holdover operating mode:

In this operating mode, the processor assembly is in the Master mode andworks without an external reference. In this operating mode, the outputof the loop filter amounts to 1.5 V.

FIG. 5 shows the monitor VCO operating mode:

In this operating mode, the output voltage value of the loop filtercorresponds to the voltage value at the VCO set voltage input. As aresult thereof, the correct output level is assured at the VCO setvoltage input at the moment of switching to the activated mode (PLLcontrol circuit) (an output level at the positive or negative detent ofthe operational amplifier would result in a frequency skip that couldlead to the upward transgression of the 5 ns maximum phase differencedemand between two processor assemblies).

Although other modifications and changes may be suggested by thoseskilled in the art, it is the intention of the inventors to embodywithin the patent warranted hereon all changes and modifications asreasonably and properly come within the scope of their contribution tothe art.

What is claimed is:
 1. A synchronization apparatus of an assembly thatgenerates a system clock signal which is synchronized to one of aplurality of reference clocks, comprising:a voltage controlledoscillator having a control input and that generates the system clocksignal of the assembly dependent on a signal at said control input; anarrangement including phase detectors each having two inputs and anoutput, a respective reference clock signal applied to one of said twoinputs of each of said phase detectors and the system clock signal beingapplied to the other of said two inputs; filters having inputs connectedto said outputs of said phase detectors and having outputs; switchesconnected at said outputs of said filters to connect signals output fromsaid filters to said control input of said voltage controlledoscillator; an operating controller connected to said switches thatcontrols said switches such that respectively one of the output signalsof the filters is through-connected to the control input of the VCO, andfurther switches connected to said operating controller which controlssaid further switches such that, given a case wherein the output signalof a respective one of the filters is not through-connected to the inputof the VCO, the output of a respective on of the phase detectors isswitched to tri-state; the output signal is fed back to a first input ofsaid respective one of said filters; and a decoupled signal of thecontrol input of the VCO is applied to a second input of said respectiveone of said filters.
 2. A synchronization unit according to claim 1,further comprising:a delay unit that delays the system clock beforeinput to a phase detector of the phase detectors by a running timedifference between the reference clock of the phase detector of thephase detectors and the system clock.
 3. A method for synchronizingclock signals in a master/slave arrangement, comprising the stepsof:generating a system clock signal depending on an input controlsignal; providing reference clock signals; detecting a phase differencebetween each of the reference clock signals and the system clock signalto obtain phase difference signals; filtering said phase differencesignals with a filter to obtain filter signals; selectively connectingone of said filter signals as said input control signal; providing atri-state output of said phase difference detecting step; feeding saidfilter signals of said filtering step back to a further filter tosynchronize said system clock to one of a plurality of reference clocks.